GARNET

원문: GARNET: A Detailed On-Chip Network Model inside a Full-System Simulator

GARNET

a detailed cycle-accurate interconnection network model inside the GEMS full-system simulation framework.

기존의 GEMS에서는 approximate interconnection model만을 제공.

이 interconnection은 set of links and nodes로 이루어져 있고, 특정 latency와 bandwidth를 설정할 수 있음

detailed router나 network interface는 제공하지 않으며

buffer contention, switch & vc arbitration, realistic link contention, pipeline bubble등은 무시.

그리고 router에서 perfect hardware multicast를 제공한다고 가정한다.

Base GARNET model design

1) State-of-the-art on-chip interconnect

five-state state-of-the-art virtual channel router

router는 topology에 따라서 any # of input, output port를 가질 수 있음

flit-level buffering rather than packet-level buffering.

Buffer Write(BW) + Route Computation(RC) -> VC Allocation(VA) -> Switch Allocation(SA) -> Switch Traversal(ST) -> Link Traversal(LT) 

2) Router microarchitectural components

Seperate VC and switch allocators. (fast and low complexity)

3) Interactions between memory system and GETNET

L1, L2 cache. Shared vs. pricate L2 cache.

4) Point-to-point ordering

message들은 보내진 순서대로 도착되어야 한다.

VC and switch allocators support system-level ordering.

5) Network power

Orion power model.

GARNET configuration and statistics